1. Field of the Invention
The embodiments of the invention generally relate to circuit design timing analysis, and, more particularly, to methods of optimizing timing of signals within an integrated circuit design using proxy slack values.
2. Description of the Related Art
Optimization transforms typically attempt to improve late (early) mode timing by speeding up (slowing down) data path delays. Unfortunately, transforms which only consider late (or early) mode slack values run the risk of making a violation in the opposite mode worse. For example, a transform which speeds up a late mode path in order to correct for a late mode slack value could end making an early mode violation worse, resulting in the need for iteration between early and late mode timing correction.
Conventional techniques require that optimization transforms explicitly check both early and late mode slack values in order to ensure that potential changes do not unexpectedly degrade results in the “opposite” mode. A large number of existing transforms exist, however, which only refer to the late mode slack values, and re-writing these to explicitly check early and late mode slacks would be extremely cumbersome. In considering both early and late timing it is also important to recognize that the delays used in these analyses are not the same (the late mode delay for an arc is larger than the early mode delay for the same arc).